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AT86RF231
Table 7-1.
State Transition Timing (Continued)
No
Symbol
Transition
Time [μs], (type)
Comments
When asserting pin 11 (SLP_TR) or TRX_CMD = TX_START
10
t TR10
PLL_ON
?
BUSY_TX
16
first symbol transmission is delayed by 16 μs delay (PLL
settling and PA ramp up)
11
t TR11
BUSY_TX
?
PLL_ON
32
PLL settling time from TX_BUSY to PLL_ON state
Using TRX_CMD = FORCE_TRX_OFF (see register 0x02,
12
t TR12
All states
?
TRX_OFF
1
TRX_STATE),
Not valid for SLEEP state
13
14
t TR13
t TR14
RESET
Various
states
?
?
TRX_OFF
PLL_ON
37
1
Valid for P_ON or SLEEP state
Using TRX_CMD = FORCE_PLL_ON (see register 0x02,
TRX_STATE),
Not valid for SLEEP, P_ON, RESET, TRX_OFF and *_NOCLK
The state transition timing is calculated based on the timing of the individual blocks shown in
Figure 7-3 on page 39 to Figure 7-7 on page 41 . The worst case values include maximum oper-
ating temperature, minimum supply voltage, and device parameter variations.
Table 7-2.
Analog Block Initialization and Settling Time
No
15
16
17
18
19
20
Symbol
t TR15
t TR16
t TR17
t TR18
t TR19
t TR20
Block
XOSC
FTN
DVREG
AVREG
PLL, initial
PLL settling
Time [μs], (type)
330
60
60
110
11
Time [μs], (max)
1000
25
1000
1000
155
24
Comment
Leaving SLEEP state, depends on crystal Q factor and
load capacitor
FTN tuning time fixed
Depends on external bypass capacitor at DVDD
(CB3 = 1 μF nom., 10 μF worst case), depends on V DD
Depends on external bypass capacitor at AVDD
(CB1 = 1 μF nom, 10 μF worst case), depends on V DD
PLL settling time TRX_OFF ? PLL_ON, including 60 μs
AVREG settling time
Settling time between channels switch
21
22
23
24
25
26
27
28
29
t TR21
t TR22
t TR23
t TR24
t TR25
t TR26
t TR27
t TR28
t TR29
PLL, CF cal
PLL, DCU cal
PLL, RX ? TX
PLL, TX ? RX
RSSI, update
ED
SHR, sync
CCA
Random value
35
96
6
16
32
2
140
140
1
PLL center frequency calibration, refer to Section 9.7.4
PLL DCU calibration, refer to Section 9.7.4
Maximum PLL settling time RX ? TX
Maximum PLL settling time TX ? RX
RSSI update period in receive states, refer to Section 8.3.2
ED measurement period, refer to Section 8.4.2
Typical SHR synchronisation period, refer to Section 8.4.2
CCA measurement period, refer to Section 8.5.2
Random value update period, refer to Section 11.2.1
43
8111C–MCU Wireless–09/09
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